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WHITE PAPER The New SiP Device Drives a Leap in RF Edge Processing mrcy.com 5 THE VERSAL® AI EDGE ACAP The RFSiP 's processing chiplet represents a new type of semiconductor architecture, an Adaptive Compute Acceleration Platform (ACAP). The Versal® AI Edge ACAP from Xilinx isn't just another FPGA or MPSoC. It 's a true heterogeneous processor, fabricated with cutting-edge 7 nm technology and incorporating three different types of compute engines. Each ACAP device includes Scalar Processors, Programmable Logic and Vector Processors, all connected by an extremely high-bandwidth network-on-chip (NoC). Multiple compute engine types are designed into the ACAP because no single style of processing is capable of optimally performing all the tasks involved in a sophisticated edge application. Scalar Processors, functioning like traditional CPUs, are ideal for complex decision-making and control. In the AI Edge ACAP, there are four of these: two low-power ARM® Cortex®-R5F real-time processors and two full-power domain Cortex-A72 cores, supported by a system memory management unit. Programmable Logic, also referred to as Adaptable Engines, adds the flexibility to handle a diverse set of computationally demanding algorithms. Included are FPGA structures, with 1.5 times the LUTs of a high-end Virtex chip, as well as programmable I/O and a customizable memory hierarchy of block RAM and UltraRAM. Vector Processors, called Intelligent Engines in the AI Edge ACAP, are optimized for advanced signal processing, such as linear algebra and matrix math, which are well suited for 5G wireless systems and AI inference. The chip contains two types: (1) DSP Engines, which function like traditional digital signal processors, and (2) AI engines, similar to advanced GPUs, comprising vector processors for fixed and floating-point operations, a scalar processor and dedicated program and data memories. In total, a single Versal ACAP chip provides 400 AI engines, 1968 DSP engines and over 900K FPGA LUTs. THE JARIET ELECTRA-MA ADC/DAC On the RFSiP, high-end processing power is combined with the extremely fast ADC/DAC capability delivered by the Jariet Electra-MA from Jariet Technologies. Each RFSiP has two of these ultra-low-power transceivers, combining to provide 4 ADC receive channels and 4 DAC transmit channels, all operating at up to 64 GS/s. They can directly digitize frequencies through 36 GHz and operate in the first Nyquist zone up to 32 GHz. THE FERRIC POWER CONVERTER The Ferric power converter is a tiny die power regulator that supports a high current density. Three of these unique chips are configured within the RFSiP, allowing it to take in just a single voltage and break it down for all the voltage rails needed by the other components. This simplified power characteristic makes for straightforward integration into larger systems. INTEGRATED INTO A TINY FORM FACTOR The Xilinx, Jariet and Ferric chips, plus 4 GB of DDR4 memory, are all integrated on an organic substrate with a tiny, 50 x 50 mm form factor. The individual chips are integrated using thermal compression bonding, which heats and compresses the dies to make connections. High-bandwidth component interconnections include a dedicated bus, which moves data directly between the Jariet ADC/DACs and the Versal ACAP. ENABLING HUGE LEAPS FOR RF EDGE APPLICATIONS The RFSiP provides direct digitization at extremely high sampling rates so systems can detect and monitor the various forms of stealthy signals. By eliminating any need for downconverting to an intermediate frequency (IF), direct digitization helps the RFSiP achieve extremely low latency responses even at 64 GS/s data rates. The RFSiP also meets the massive processing requirements for low- latency responses and for tracking all manner of potential targets, including those moving at hypersonic speeds. Versal AI Core. Source: Xilinx

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