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Application Note PBGA THERMAL RESISTANCE CORRELATION 1 Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com Mercury Systems reserves the right to change products or specifi cations without notice. © 2016 Mercury Systems. All rights reserved. AN0019.02E-0916-an PBGA THERMAL RESISTANCE CORRELATION INTRODUCTION The thermal resistances for the Plastic Ball Grid Array (PBGA) Multi Chip Packages (MCP) published in WEDC data sheets are results from thermal modeling software calculations. This paper explains how the simulation results were correlated to actual measured values. DEFINITIONS P D (W) =Total package power dissipation T J (°C) =Junction Temperature T A (°C) = Ambient Temperature T T (°C) = Top case Temperature T B (°C) = Board Temperature JB (°C/W) = Junction to Board thermal resistance defi ned as (T J - T B )/ P D JC (°C/W) = Junction to Case thermal resistance defi ned as (T J - T C )/ P D JA (°C/W) = Junction to Ambient thermal resistance defi ned as (T J - T A )/ P D JT (°C/W) = Junction to Top case thermal resistance defi ned as (T J - T T )/ P D SCOPE The thermal modeling software was specifi cally designed for silicon packages such as these multi-chip PBGAs. The thermal modeling uses design entries such as mechanical dimensions, die placement and thickness, thermal material properties, ball amount and placement, etc. The calculations provide three thermal resistances that are used in user's applications to determine maximum junction temperature, and then the need to use cooling techniques if necessary. The three thermal resistances are Junction to Ambient ( JA ), Junction to Board ( JB ), and Junction to Case ( JC ) thermal resistance as defi ned per JEDEC JESD51 specifi cations. Note: Junction to Top case thermal resistance ( JT ) is not provided since by defi nition top case temperature is taken at the top center of the package. Since these MCPs usually do not have die in the center it doesn't represent worst case. The maximum Junction to Case thermal resistance ( JC ) of the die with the biggest resistance value is published. CALIBRATION, MEASUREMENTS AND MODELING The WEDPN8M72V-XBX SDRAM device was chosen as the test vehicle since it is represents a typical large BGA package. The device is a multi-chip plastic BGA package that contains fi ve 128Mb SDRAM memory die. External dimensions are 25mm x 32 mm with 219 balls on a 1.27mm pitch. See mechanical Outline per fi gure 1. Using JEDEC JESD51 specifi cation method, the devices were mounted on a 101.60 x 114.30mm 1.60mm thick 4-layer board (see Figure 2). Actual production devices with functional die (vs. thermal die) were used for test, where the parallel combination of the Vcc/Gnd reversed bias of all die were utilized as the heating source. Calibration: The forward-voltage drop of the parallel combination of Vcc/Gnd reversed bias of the chips was used as the temperature sensitive parameter. The electrical method of junction temperature measurement is based on a temperature and voltage dependency exhibited by all semiconductor diode junctions. This relationship, often referred to as the Temperature Sensitive Parameter (TSP) slope can be measured and used to compute the semiconductor junction temperatures in response to power dissipation in the junction region. These measurements were performed in a dielectric oil bath under unpowered, thermal equilibrium conditions so junction and case temperature are nearly equal. Measurements: Temperature measurements were performed per JEDEC JESD51 specifi cations on 10 devices. Using equations from defi nitions, the thermal resistance was calculated: JA had an average of 13.3°C/W with a maximum of 13.9°C/W JB had an average of 8.8°C/W with a maximum of 9.2°C/W JT had an average of 1.3°C/W with a maximum of 1.9°C/W Modeling Results: JA = Average 13.96 °C/W with a maximum of 14.3°C/W JB = Average 9.93 °C/W with a maximum of 10.4°C/W JT = Average 2.17 °C/W with a maximum of 2.6°C/W

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