Issue link: https://read.uberflip.com/i/1173434
www.mrcy.com INNOVATION THAT MATTERS ® Corporate Headquarters 50 Minuteman Road • Andover, MA 01810 USA (978) 967-1401 • (866) 627-6951 • Fax (978) 256-3599 advanCed MiCroeleCtroniCs Center 3601 East University Drive • Phoenix, AZ 85034 USA (602) 437-1520 Mercury Systems and Innovation That Matters are registered trademarks of Mercury Systems, Inc. Other products mentioned may be trademarks or registered trademarks of their respective holders. Mercury Systems, Inc. believes this information is accurate as of its publication date and is not responsible for any inadvertent errors. The information contained herein is subject to change without notice. Copyright © 2019 Mercury Systems, Inc. 3466.00E-1118-wp-AI The path to military-grade DDR5 With expected double bandwidth and density over DDR4 along with improvements to power and channel efficiency, advanced edge processing architectures will utilize DDR5 devices to increase performance. However, even with Mercury's advancements in the coplanar topology for a high- density multi-chip package previously discussed, the higher data speeds for DDR5 still cannot be attained. Further improvements to crosstalk performance and the inter-die network are necessary. Developing a unique multi-planar ground and signal trace layout applied to the RDL increases crosstalk isolation resulting in a performance improvement of 6 dB. No other known die stacking design methodology is available today for the commercialization of high-density DDR5 in a singular device with data rates up to 6400 Mbps. With the DDR5 JEDEC standard still in development, commercial DDR5 devices are set to release in 2019. Mercury's military-grade, high-density devices supporting speeds up to 6400 Mbps using our new advanced topology techniques will follow shortly after with release in 2020. Designers and users of next-generation military edge processing systems will soon realize the maximum performance of their high-speed multi-core edge processing systems due to the integration of high capacity, high- speed stacked DDR5 while simultaneously benefiting from a much smaller system footprint. To learn more about high-density, military-grade DDR4 and DDR5 and custom microelectronic devices for edge processing architectures in intelligent sensor systems, contact Mercury Systems at secure.memory@mrcy.com. Table of Acronyms AI Artificial Intelligence DDR4 Double-Data Rate Fourth Generation DIMM Dual Inline Memory Modules ECC Error Correction Code FPGA Field Programmable Gate Array ISR Intelligence, Surveillance and Reconnaissance MCM Multi-Chip Module RDL Redistribution Layer SI Signal Integrity SNR Signal-to-Noise Ratio SWaP Size, Weight and Power TEM Transverse Electromagnetic UAV Unmanned Aerial Vehicle UGV Unmanned Ground Vehicle UI Unit Interval About the Authors Jennifer Keenan is the Senior Product Marketing Manager for the Microelectronics Secure Solutions group in Phoenix, Ariz. Jennifer has a Bachelor's Degree in Marketing from Florida State University. Seann Ayers is the Senior Principal Signal Integrity Engineer for the Microelectronics Secure Solutions group in Phoenix, Ariz. Seann has a BSEE from Wentworth Institute of Technology and has completed graduate courses in electrical engineering at Southern Methodist University. Figure 9. 6400 Mbps DDR5 using advanced multi-planar topology Branch -20 -10 0 10 20 30 40 Co-planar Multi-planar Crosstalk Return Loss Figure 10. Crosstalk and return loss performance using branch, co-planar and multi-planar topology 16mm 23mm 3.73mm Figure 8. High-density 16GB DDR4 with ECC