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FPGA Power Modeling

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w w w. m r c y. c o m WHITE PAPER For example, consider a hypothetical scenario describing the development of a new EW system. In order to apply proprietary digital signal processing (DSP) algorithms to a received signal, the system designer needs a high-performance FPGA module that consists of multiple FPGA devices and supporting circuity. The engineer selects an off-the-shelf FPGA module by comparing its processing specifications to the calculated system need. Six months into the development process the proprietary DSP algorithms are installed on the FPGA module and the module is integrated into the system. However, during testing it is found that the current draw of the FPGA module is higher than anticipated, indicating possible overheating of the FPGA devices. Through additional analysis, the engineer determines that the device is running significantly hotter than specified. The development team now must weigh the risk of a possible field failure resulting from the increased junction temperature against the time and cost of procuring a new FPGA module. In the above example it is completely possible that the FPGA module was fully tested by the supplier and met all requirements. It is also possible that this same module was adequate to support a different customer's system. However, since the module's power dissipation is dependent on the specific algorithm, a more processing-intense application could cause the FPGA devices to generate more heat than the module can safely dissipate. These new thermal constraints require a new design methodology on the part of the FPGA module supplier. No longer can the designer simply utilize the latest FPGA devices and make some reasonable assumptions regarding the power dissipation. In order to develop high-performing FPGA modules designers now must address power dissipation from the earliest design phases and incorporate accurate thermal modeling techniques that include an understanding of the end user's algorithm. Key Power Dissipation Drivers in Modern FPGA Devices As previously stated, modern FPGA devices dissipate more thermal power than older devices. Looking at a single gate, the power dissipation is roughly equal to the product of the device capacitance, voltage swing squared, operating frequency, and bit toggle rate. While we would expect some decrease in device capacitance for smaller, more modern devices, the operational frequency tends to increase thereby leading to a higher power density. Additionally, since new devices contain more gates, the total power dissipation is far greater. Power ≈ freq*C*V 2 *R toggle A second contributor to the increased power dissipation in modern FPGA devices results from the higher levels of leakage current. Even if only a small portion of a large FPGA device is used, this high quiescent current causes significant power dissipation. The Growing Role of Processing Technology in Electronic Warfare Systems As described by Moore's Law, the exponential increase in processing power is impacting nearly all industries. Components such as custom application specific integrated circuits (ASICs) microprocessors, microcontrollers and field programmable gate arrays (FPGAs) are becoming faster and increasingly available. On the commercial side, we see this technology enabling new applications such as the internet-of- things (IoT) and self-driving cars. In the aerospace and defense industry, this digital transformation is driving a wide range of technologies and enabling new types of systems. One critical example of the application of this digital transformation is the technology advancement in low-latency, high-performance modules. These modules provide the front-end digitization and low-latency processing required to develop the electronic warfare (EW) systems that ensure control of the electromagnetic spectrum (EMS). However, these processing advancements are not limited to the US and allies. Through application of commercially available technologies, rival nations are also developing the tools to gain control of the EMS. Without the ability to freely operate across the EMS, the warfighter has limited access to technologies often taken for granted such as GPS navigation, radar and secure communication. Mitigating these emerging threats and maintaining spectrum superiority requires the development of high-performance systems that not only incorporate the latest processing technologies but are small enough to deploy in demanding size, weight and power (SWaP)-constrained environments. In order to achieve this performance and customization in a compact form factor, these products often rely on FPGA modules. With the ability to integrate digitization capabilities both on-chip and off-chip, these modules are ideal for digitizing, processing and transmitting complex signals. For example, a digital RF memory (DRFM) system often use this approach to receive, process, and transmit radar signals with extremely low latency. As new threats push the boundaries of EW hardware, the processing demands on these FPGA modules increases. Power Dissipation – a New Limiting Factor Historically the advancements in FPGA technology have supported each new generation of high-performance EW system. However, in the last few years a new limiting factor in FPGA performance is emerging. While modern FPGA devices have the size and speed to support processing- intensive EW and radar algorithms, they are unusable if the system fails to manage the heat generated by the devices. Additionally, since the power usage depends on the specific algorithm installed on the FPGA, it is possible that this limitation is not discovered until the FPGA module is integrated into the customer's system. The consequences of poor thermal management are often severe. For borderline cases, the mean-time-between-failure (MTBF) is reduced, increasing the likelihood of the module failing in the field. For more severe cases, the FPGA module will be unable to handle an intensive algorithm. Additionally, poor power modeling can lead to the design of a power supply that is unable to provide sufficient current to the FPGA devices. 2

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