White Paper

w w w. m r c y. c o m WHITE PAPER 4 Early Power Prediction Modeling By adhering to a design framework, we leverage the results of previous modeling activities to determine the inputs to our modeling tool. This provides an accurate estimation of the power dissipation as a function of various parameters. Hardware Design and Prototype Build The results of the early power prediction modeling are passed to a mechanical team for the design of the cooling solution as well as the hardware team for the design of the power supplies and circuit board assembly. Prototype hardware is built and, due to the accuracy of the preliminary modeling, typically performs well. Power Validation Testing Since the power usage of the FPGA module is highly dependent on the specific algorithm, validating the accuracy of the model requires a deep understanding of the end user's processing requirements. In order to perform this measurement, we have developed proprietary IP that has been optimized to accurately represent various types of algorithms— such as the ones used for radar, electronic attack, and spectrum management applications. Correlation Based on the results of the validation testing, we improve the accuracy of the assumptions that were used to generate the early stage power estimation. Since many of the inputs to other early stage power estimation model are very similar for a given design framework, they can be applied to future designs. This process continually improves the accuracy of the model, maximizing the first-pass design success. A graphical representation of FPGA module temperature based on Mercury's FPGA power modeling Mercury's Early Power Prediction Modeling Tool In order to apply the results of one modeling activity to a subsequent design, the early power prediction tool must simplify the process of entering the various parameters into the model supplied by the FPGA device manufacturer. However, accuracy must not be sacrificed for the sake of efficiency. The Mercury modeling tool achieves this balance by taking the power model as provided by the FPGA device manufacturer and adding automation to generate the various inputs. By separating the FPGA logic into groups based on function, it simplifies the process of defining the inputs to the model. CONTROL PLANE SAMPLE DATA STREAM INTERFACES STREAM DATA CONTROL INTERFACES CONTROL PLANE CONTROL PLANE CONTROL PLANE CONTROL PLANE CONTROL PLANE SAMPLE PROCESSING CONTROL INTERFACES STREAM INTERFACES CONTROL INTERFACES SIM SPM DPM TIM TCM CPM SAMPLE PROCESSING CLOCKS & SYNCS Modeling divides FPGA in functional blocks Additionally, we reuse a common architecture across multiple FPGA module designs, including a consistent but scalable control-plane infrastructure, proven data-plane infrastructure (interfaces, framers, & switches), and standard clocking and synchronization IP. The FPGA design blocks are partitioned based on their properties; such as sample data, sample processing, stream data, control plane, stream interfaces, etc. By reusing this proven infrastructure and modeling design blocks according to their respective properties, we iteratively improve the accuracy of the modeling. Since this tool uses automation to populate the manufacturer's model, it enables rapid design automation through parameter sweeping. Additionally, it allows us to optimize a model to converge on measured data in order to improve the accuracy of the inputs to the model for future designs. EchoCore™ Design Validation As previously discussed, both modeling the FPGA power usage and validating the hardware requires a deep understanding of the customer algorithm. Since different applications vary in complexity and result in different bit toggle rates, the power validation is specific to individual use cases. To achieve this flexibility, Mercury has developed the EchoCore™ Power Load IP. This technology allows precise control of FPGA resource utilization and has been shown to correlate well with various customer algorithms.

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