White Paper

Understanding Broadband Electrical Behavior of Through-Silicon Via (TSV)

Issue link: https://read.uberflip.com/i/1233873

Contents of this Issue

Navigation

Page 3 of 7

w w w. m r c y. c o m WHITE PAPER 3 By calculating the silicon dielectric relaxation frequency from Equation 1, assuming a 10 Ω/cm bulk resistivity, the silicon relaxation frequency is ~15.1 GHz. Extracting the S-Parameters of the equivalent RLGC network in Figure 2, we can inspect the S21 insertion loss plot to quantify the magnitude and frequency span of the SWM, as well as correlate the SWM transition with respect to the calculated dielectric relaxation frequency. The "knee" frequency of the insertion plot (~15 GHz) closely correlates to the silicon relaxation frequency (15.1 GHz), which signifies the end of SWM (Figure 3). Digging a little deeper, by "unwrapping" the phase of the insertion loss (S21), the signal flight times with respect to frequency can be extracted. This allows simple approximation of the magnitude of flight-time delta with respect to frequency. At the silicon relaxation frequency (15.1 GHz) the flight time is only 731 fs, a reduction of approximately 40% (Figure 4). Figure 4. Silicon relaxation frequency (~15 GHz) Figure 3. Frequency of the insertion plot (~15 GHz)

Articles in this issue

view archives of White Paper - Understanding Broadband Electrical Behavior of Through-Silicon Via (TSV)