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INNOVATION THAT MATTERS
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8030.02E-0520-wp-TSV.indd
CONCLUSION
It's imperative to fully understand the broadband electrical performance
of a given TSV structure. More specifically, SWM, which needs to be fully
understood in order to successfully mitigate potentially catastrophic group
delay in applications where group-delay "flatness" is critical. Utilizing a
high bulk-resistivity silicon is one of the easiest methods to mitigate the
unwanted effects of SWM.
About the Author
Seann Ayers is the Senior Principal Signal Integrity Engineer for the
Microelectronics Secure Solutions group in Phoenix, Arizona. Seann has a
BSEE from Wentworth Institute of Technology and has completed graduate
courses in electrical engineering at Southern Methodist University.
