White Paper

Redefining Sensor Edge Processing with 2.5D System-in-Package Technology

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2 www.mrcy.com Figure 3: Demonstration of space-saving capability of SiP technology To overcome these limitations, modern designs must move away from a centralized computing model and put the processing where the data is—at the sensor edge. Implementation Challenges at the Sensor Edge Implementing sensor-edge processing requires multiple, tightly integrated RF and digital functions to manage and manipulate the data flow. Transceivers, connected directly to an antenna, capture the data in analog form, then move it to analog-to-digital converters (ADCs) that transform it into a digital bitstream. The digital data is then processed by either a field programmable gate array (FPGA) or a general purpose processor, or both, and, if an electronic response is required, the signal is then moved back through digital-to-analog converters (DACs) to the transceiver and, finally, the antenna. All these integrated functions must be packaged in a small and rugged form factor so they can be placed near the sensor, whether at a wingtip, in a small unmanned aerial vehicle (UAV), or on a Humvee's hood. These types of deployments, operating in exposed and harsh environments, clearly require that the sensor-edge processing is designed and packaged to withstand shock, vibration, and temperature extremes. The sensor-edge deployments also place rigorous constraints on the SWaP of the processing package; the most obvious example is a micro air vehicle, where the entire flying platform is smaller than a traditional embedded computer. Monolithic, Many-Core Silicon Won't Work on the Edge Some time ago, semiconductor technology reached the point where cycle frequency, which drives the performance of any individual processing core, became stagnant. The only way to increase overall chip performance is to add more and more functionality to each chip, essentially adding more cores. This works if the application is a server farm, but not at the tactical edge where SWaP is key. While today's many-core processors can execute billions of instructions per second, they are not designed for optimal power use. In fact, the extra circuitry needed to control and coordinate 16 or more computing cores adds significantly to a chip's power requirements, so that performance per watt has actually decreased over time. High power use translates into a high cooling burden, which is not a significant issue in an air conditioned room, but a real problem for embedded systems. Another drawback for many-core embedded use is the overhead required to parcel out real-time processing across large numbers of cores. This adds to latency and, in some applications, is just not practical. For sensor applications, many-core processors must also be supported by specialized mixed-signal application-specific integrated circuits (ASICs) and dedicated security processors. A complete radar or EW solution becomes, by necessity, a board-level device with multiple individual components addressing digitization, security, and processing. Applying many-core silicon becomes even more complicated if a platform requires safety certification. As the number of cores increase, the number of interactions between cores goes up geometrically for even basic tasks like memory transfers. It becomes almost impossible to prove safe operation for all possible combinations of interactions. Instead of board-level solutions, some edge-processing applications leverage custom-designed, mixed-signal ASIC technology. While a customized semiconductor component allows maximum SWaP optimization, it also requires performance trade-offs in analog bandwidth. Additionally, a custom ASIC is also extremely expensive and has a five- to seven-year development cycle, making it an ineffective solution in today's rapidly evolving defense environment. Given all these drawbacks to many-core processing and custom ASICs, it is not surprising that embedded designers are looking for a better approach to meet the requirements of sensor-edge computing. They need SWaP-optimized chip-scale implementations with new levels of performance per watt, tight integration between analog and digital functions, and a straightforward path to customization for specific application requirements, including unique frequency ranges. FPGA RF DSP STACKED MEMORY Traditional Surface-Mount Solution BGA-Packaged Devices Multiple Die Si Interposer Organic Substrate 2.5D System-in-Package Design FPGA RF DSP STACKED MEMORY Fully Assembled Printed Circuit Board (PCB) FPGA RF DSP STACKED MEMORY Up to reduction in board size 80%

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