White Paper

Redefining Sensor Edge Processing with 2.5D System-in-Package Technology

Issue link: https://read.uberflip.com/i/1263446

Contents of this Issue

Navigation

Page 3 of 5

w w w. m r c y. c o m WHITE PAPER 3 A Flexible Approach to Semiconductor Design Heterogeneous 2.5D SiP technology is a powerful new trend in microelectronics. This design approach integrates individual intellectual property (IP) blocks called chiplets, as opposed to a monolithic solution where all the functionality is contained in a single semiconductor device. The IP in a chiplet performs a specific function, such as RF capture and transmission, ADC/DAC conversion, digital I/O, FPGA-based digital signal processing, or any one of the dozens of tasks needed to implement a mixed-signal data flow. Each chiplet is an individual semiconductor, so that even the material can be optimized for its function. For example, the designer can select a silicon process for a processing-intensive FPGA and a silicon-germanium process for high-frequency ADC/DAC blocks. To develop an application-specific solution, the chiplets are integrated into a functioning whole by mounting them onto a custom piece of silicon called the interposer, which includes high-density, through-silicon via technology for transmitting signals between the chiplets and out of the package. Each IP chiplet is a reusable component—designed, developed, and tested to perform its specific function by separate teams at various times and often by different companies. The only custom component in a 2.5D SiP design is the interposer, where there are significant technical challenges. Within the interposer, a variety of high-frequency signals must be routed between chiplets in a small space, while minimizing cross talk and other threats to signal integrity. Unfortunately, the electrical behavior of these signal connections over a broad range of frequencies is very unpredictable due to the non-linear behavior of silicon. Overcoming the resulting challenges requires specialized expertise and fabrication equipment. However, because it consists only of interconnects and no logic, an interposer can be laid out and fabricated much more quickly than a monolithic ASIC. In addition, the development cost for each chiplet can be spread across all the 2.5D SiP implementations where it is used. These two advantages, faster time to market and lower total costs, are making 2.5D SiP technology a preferred approach for many commercial applications (see Figure 5). 2.5D Integrates at the Sensor Edge 2.5D SiP components are also proving to be an excellent match for sensor-edge processing requirements. Mixed-signal designs for radar and EW, which combine both analog RF and digital circuits, map well into combinations of IP chiplets. 2.5D SiP designs can flexibly select CPUs, GPUs, and FPGAs and apply each where it fits best in a specific application's processing chain, then combine them with transceivers and ADC/DAC components that match the targeted RF band. New high-performance chiplets support direct digitization of wideband RF signals, achieving the high fidelity needed for next-generation radar and EW systems. In addition, the chiplets are in close proximity, communicating via the high-density interconnects within an interposer. This reduces both latency and physical size. A final advantage worthy of attention is the outstanding SWaP characteristics possible with a 2.5D SiP technology approach. All the compact chiplets are mounted on a single silicon interposer, with no unnecessary cores or processing overhead. Small size, low weight, and minimal power are all hallmarks of 2.5D SiP solutions. Current designs put the functionality of a 6U OpenVPX™ board into a form factor smaller than a business card. Beyond the Technology Advantages While its technology advantages are clear, 2.5D SiP designs also offer important program-level advantages. First, a new sensor-edge processing project can design, fabricate, test, and deploy a customized, 2.5D SiP solution in two or three years, compared to the five- or seven- year time frame of a custom ASIC. Figure 4: Size of SiP device compared to human hand. Figure 5: New system-in-package technology enables accelerated delivery cycle and rapid customization.

Articles in this issue

view archives of White Paper - Redefining Sensor Edge Processing with 2.5D System-in-Package Technology