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Tackling workloads in real time with PCIe Gen 4.0
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More Details on the PCIe Standard
PCIe is a standard defining communication
between two devices over a point-to-point
interconnect, or link, with each link having one
or more lanes. Every lane has two signaling
pairs, one pair for receiving and one for
sending; that means every lane consists of
four physical wires, or semiconductor traces.
The PCIe standard defines links with 1,
4, 8, 16 or 32 lanes, though 32-lane links
are rare. The lane count is written with an
'x', so a 16-lane link is 'x16'. Lane count is
often called 'width,' as in '16 lanes wide.'
There are two different ways of measuring the
performance of a specific link. One way uses the
raw bit-transfer rate, usually expressed in terms
of 'gigatransfers per second' (GT/s). The other,
more useful measure reflects the effective
transfer rate of actual data, or bandwidth. The
data bandwidth is less than the raw transfer rate
because a portion of the bits transferred are
used to ensure data integrity (encoding) and for
other communication overhead tasks. The chart
below shows these two measurement values
per single lane for PCIe versions 1 through 6.
As this chart makes clear, the available data bandwidth doubles for each successive generation.
Regarding system upgrades, PCIe 4.0 motherboards are backwards compatible with all 3.0 devices.
However, PCIe 4.0 devices must be used at both ends of a communication path in order to get full
benefit from technology.
GENERATION BANDWIDTH (X16) GIGATRANSFER INTRODUCED
PCIe 1.0 4 GB/s 2.5 GT/s 2003
PCIe 2.0 8 GB/s 5 GT/s 2007
PCIe 3.0 16 GB/s 8 GT/s 2010
PCIe 4.0 32 GB/s 16 GT/s 2017
PCIe 5.0 64 GB/s 32 GT/s 2019
PCIe 6.0 128 GB/s 64 GT/s 2021 (Est.)
