Product References

3 OpenFPGA: RAPPID FIRMWARE App-based electronic warfare mrcy.com OpenFPGA BENEFITS It 's critical to provide complex solutions to customers in less time and with reduced vendor lock. OpenFPGA provides several benefits to the development, deployment and sustainment phases of a program. Using a common design methodology, system designers can implement their solutions with less concern regarding the chosen FPGA hardware because the OpenFPGA framework provides an open and standard FPGA resource interface to the user. OpenFPGA-developed solutions are rapidly implemented regardless of FPGA hardware, and smoothly ported to any OpenFPGA-supported hardware device. FPGA resources are commonly in short supply and larger FPGAs are constantly being produced. Customers are continually asked to add more capability to the FPGA which increases the cost and introduces thermal dissipation challenges. This results in a significant amount of time and effort spent in the FPGA design process to fit the algorithm into the FPGA device. OpenFPGA concept, supporting multiple FPGA boards OpenFPGA concept, partial reconfiguration of user capabilities OpenFPGA concept block diagram By using OpenFPGA, and the RAPPID open platform, EW techniques can be dynamically swapped in and out as needed in real time, maximizing system performance. As new techniques are developed or needs change, they can be loaded into the FPGA where they can be accessed quickly to support low-latency operation. This allows a smaller, less expensive FPGA and simplifies the cooling requirements since it dissipates less power. With the flexibility continuing post-deployment, there are benefits of sustainability, upgradeability and lower overall system cost. In addition, OpenFPGA supports the complete and partial reconfiguration of an FPGA to recognize greater efficiencies. When spectrum processing capabilities are not required to operate simultaneously, they can be loaded into the FPGA at separate commanded times, allowing more capability to fit into the same FPGA and substantially increasing the amount of solutions available during deployment. An example of this is described in the use cases that follow. The common interfaces and partial reconfiguration act as building blocks to load application-specific IP blocks to the FPGA processor. This absorbs the burden of upgrading next-generation FPGA devices, and by creating a common interface to FPGA resources, PCIe interfaces, off-FPGA and general purpose I/O, OpenFPGA removes the learning curve associated with vendor board-support packages (BSPs). EW designers are being asked to provide complex solutions to their end users in less time, while moving away from the "vendor-locked" solutions of the past. Vendor 1 FPGA Vendor 2 FPGA Vendor 3 FPGA User FPGA Logic Same Logic Multiple Devices FPGA Processing Board User FPGA logic OpenFPGA Wrapper Vendor Board Support Package FPGA Processing Board PCIe Interface (Static) Command and Control (Static) Clock Management (Static) User FPGA Capability 1 User FPGA Capability User FPGA Capability 2 User FPGA Capability User FPGA Capability N User FPGA Capability DATA IN DATA IN DATA OUT DATA OUT CLOCKS CLOCKS PCIE MEMORY STATUS COMMAND CLOCKS CLOCKS PCIE MEMORY STATUS COMMAND

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