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Memories with Extended Temperatures
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Redesigned tables
MEMORIES WITH EXTENDED TEMPERATURES
DDR4 SDRAM MCP
Size Organization Part Number Data Rate (Mb/s) Voltage (V) Package Dimensions Temperature
4 GB 51 x 72 4N512M72T-XB2X 1600–-2400 1.2 321 PBGA 13 mm x 20 mm C, I, M
8 GB 1G x 72 4N1G72T-XB2X 1600–2400 1.2 321 PBGA 13 mm x 20 mm C, I, M
16 GB 2G x 72 4N2G72T-XB2X* 1600–2666 1.2 367 PBGA 16 mm x 32 mm C, I, M
DDR3 SDRAM MCP
Size Organization Part Number Data Rate (Mb/s) Voltage (V) Package Dimensions Temperature
1 GB 128M x 64 W3J128M64X-XLBX 800–1600 K=1.35, G=1.5 375 PBGA 20.5 mm x 21.5 mm C, I, M
1 GB 128M x 72 W3J128M72X-XLBX 800–1600 K=1.35, G=1.5 375 PBGA 20.5 mm x 21.5 mm C, I, M
2 GB 512M x 32 W3J512M32X(T) -XB3X 800–1333 K=1.35, G=1.5 204 PBGA 10 mm x 14.5 mm C, I, M
2 GB 512M x 32 W3J512M32X-XB3X 800–1600 K=1.35, G=1.5 136 PBGA 10 mm x 14.5 mm C, I, M
4 GB 512M x 64 W3J512M64X-XLB2X 800–1600 K=1.35, G=1.5 543 PBGA 23 mm x 32 mm C, I, M
4 GB 512M x 72 W3J512M72X-XLB2X 800–1600 K=1.35, G=1.5 543 PBGA 23 mm x 32 mm C, I, M
4 GB HD 512M x 72 W3J512M72X(T) -XHDX 800–1600 K=1.35, G=1.5 399 PBGA 14 mm x 21.5 mm C, I, M
8 GB 1G x 72 W3J1G72KT-XLBX 800–1600 K=1.35, G=1.5 543 PBGA 23 mm x 32 mm C, I, M
DDR2 SDRAM MCP
Size Organization Part Number Data Rate (Mb/s) Voltage (V) Package Dimensions Temperature
128 MB 64M x 16 W3H64M16E-XB2X 400–667 1.8 79 PBGA 11 mm x 14 mm C, I, M
256 MB 2 x 64M x 16 W3H264M16E-XSBX 400–667 1.8 79 PBGA 11 mm x 14 mm C, I, M
256 MB 2 x 64M x 16 W3H264M16E-XB2X 400–667 1.8 79 PBGA 11 mm x 14 mm C, I, M
256 MB 32M x 64 W3H32M64E-XBX 400–667 1.8 208 PBGA 16 mm x 20 mm C, I, M
256 MB 32M x 72 W3H32M72E-XBX 400–667 1.8 208 PBGA 16 mm x 20 mm C, I, M
512 MB 64M x 64 W3H64M64E-XBX 400–667 1.8 208 PBGA 16 mm x 22 mm C, I, M
512 MB 64M x 72 W3H64M72E-XBX 400–667 1.8 208 PBGA 16 mm x 22 mm C, I, M
1 GB 128M x 72 W3H128M72E-XSBX 400–667 1.8 208 PBGA 16 mm x 22 mm C, I, M
1 GB 128M x 72 W3H128M72E-XNBX 400–667 1.8 208 PBGA 16 mm x 22 mm C, I, M
DDR PERFORMANCE, LAYOUT AND DESIGN BENEFITS
▪ Reduce board real estate, I/O
requirements and memory down
routing by up to 70%, permitting
additional product options and
board design opportunities.
▪ Save 2–4 PWB layers and cut design
time up to four weeks by reducing
memory down routing.
▪ Improve parasitic performance (L, pu, C)
at first and second levels with reduced
bus capacitance and better signal
integrity on the PCB.
▪ Obtain wider pitch on BGA leads
with reduced I/O and routing for easier
class-3 PWB rule compliance.
▪ Minimize maintenance costs with
consistent MCP interface, despite
part obsolescence issues.
* Advanced product — This product is developmental, is not qualified and is subject to change or cancellation without notice.
