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8107.00E-0322-wp-ACAP-Journey_FINAL

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WHITE PAPER Designer's Journey: Navigating the Transition to Versal ACAP mrcy.com 8 MULTI-KERNEL GRAPH So far, we have explored several example AIE kernels. But what about larger applications? To effectively use the AIE array, designers must consider how to divide their application into multiple kernels that work together. To demonstrate this, we created a graph with 16 kernels where each of the kernels computes part of the input elements. The intermediate results are passed to the next kernel in the AIE array through a cascade path. The last kernel finishes the calculations and outputs the data to the FPGA fabric. Multi-Kernel Graph HIGH-PERFORMANCE APPLICATIONS For the most demanding applications, designers should consider how to structure graphs so they can scale efficiently across many AIEs. The physical location of kernels and I/O interfaces is also important. A good starting point is to map the dataflow of the application, as this will guide the other aspects of the AIE design. Input data should flow directly upward from the logic fabric through the AIE array. This is because the AIE array 's AXI4-Stream interconnect is non-symmetrical, with more paths traveling north than any other direction (see the AIE Array Diagram on page 3). If one of the input streams is broadcast to many kernels, it will occupy more routing as it branches out to each of the destinations. Within the application, designers should take advantage of the cascade path to forward data between kernels when possible. To transfer low-bandwidth data, designers should consider using RTPs, which can be transferred both between kernels as well as the processing system. These techniques will reduce the total number of data streams and make the application more flexible and easier to implement.

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