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White Paper: Processing Evolution Future Battlespace Approaches

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WHITE PAPER Processing Evolution for the Future Electronic Battlespace mrcy.com 6 NEXT GEN RF PROCESSING TECHNOLOGY To realize the high-performance capabilities of next generation RF systems, a portfolio of technologies is needed to architect application-optimized MFRF processor designs. However, it 's not sufficient to simply have the building blocks. Just as important as the technology components themselves is the infrastructure and expertise to integrate all the building blocks, backplanes and chassis into powerful subsystems, tested and environmentally qualified for field survival. For instance, an airborne MFRF processing solution may include a full range of processors and computing styles, including highly-programmable datacenter-class CPUs, FPGAs/ACAPs, and GPUs, ruggedized for deployment in the harshest environments: ▪ Datacenter-class CPUs – The most powerful Intel® Scalable Processors (SP) deployed onto rugged, open architecture form factors that enable the next generation of complex sensor data processing and sensor control processing at the edge. ▪ Advanced GPU architectures – NVIDIA® GPUs implemented on a single 6U OpenVPX board allow RF system developers to deploy their image processing and AI applications to the rugged edge. NVLINK provides for further optimizations and ease of programmability to help bring emerging AI algorithms to reality, quicker. ▪ Emerging ACAPs – Heterogeneous processors, like the Versal™ AI Core ACAP from Xilinx®, fabricate multiple types of compute engines within a single chip to improve processing speeds up to 20× compared to the fastest FPGA implementations available today – perfect for early-stage signal conditioning processing. In addition to the advanced processing technologies, above, high-bandwidth ingest and interconnects ensure data movement keeps pace with wide bandwidth sensors and the new accelerated forms of processing. Support for PCIe Gen5 and 100/200/400 GbE in both integrated silicon and processing subsystem backplanes, along with optical I/O is essential.

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