White Paper

WHITE PAPER A Generational Leap in Edge Computing with the Versal® ACAP mrcy.com 5 Keep the Data Moving Having a variety of processing engines is only useful if they are processing data in parallel and not stalled, so managing I/O bottlenecks is critical. ACAPs use a hardened NoC that can be programmed to suppor t flexible data flows between the full range, high-speed I/Os and the various types of computing engines. The NoC programmability extends to addressing different levels of throughputs, latencies, and even bit widths in the event of multiple algorithms on a single chip being optimized for different resolutions. Functionally, the NoC is a packet switch network that per forms high-speed, point-to-point hops to move data around the device. Even without exploiting its inherent parallelism, the NoC is capable of data bandwidths exceeding 2Tb/s, with much greater data movement capacity if the application design mapping exploits parallelism. This level of on-chip bandwidth is critical for low-latency per formance in applications like AESA radar that must process multiple data streams concurrently, as well as complex AI-enhanced EW applications that first use FPGA structures in applying signal processing algorithms to a captured signal and then must move the processed data to an AI Engine where other algorithms implement analysis and response. A High-Performance Memory Hierarchy Similar to avoiding I/O bottlenecks, high-per formance memor y access is critical to ensuring that applications can deliver a low latency, deterministic response. The ACAP addresses this with an on-chip cacheless memor y hierarchy consisting of block RAM, UltraRAM, and accelerator RAM; all levels of the hierarchy are essentially shared RAM. The accelerator RAM, introduced in the Versal AI Core series, enables storage of multiple application datasets directly on-chip, reducing both power consumption and latency by avoiding off-chip memor y accesses. The ACAP 's expansive on-chip memory structure is well suited to manipulating and analyzing large imagery data sets. Examples include applications using AI deep-learning techniques for facial recognition or object identification. ACAPS AND AI AT THE EDGE For defense systems, perhaps the most exciting feature in ACAP is that its Intelligent Engines will suppor t adding AI capability to a host of edge applications. The section 'Processing for Complex Applications' discusses one example, enhancing EW applications with AI that can create low-latency countermeasures while located adjacent to an antenna at the tactical edge. This type of application is often referred to as Cognitive EW. Similar forms of advanced new functionality, powered by AI, can be envisioned across a range of applications. Image recognition located next to the optical and infrared sensors in perimeter security systems is one example. Voice recognition attached to microphones would fur ther enhance these systems. Another image recognition example involves UAV data collection. For example, a sur veillance UAV may fly an 18-hour mission, imaging disputed terrain, with only 5 minutes of that imaging showing anything of interest to analysts. Having an onboard AI capability that could identify, extract, and transmit that small section of collected data would enable better command decisions and faster responses. Wholly new applications will also become possible. Autonomous ground vehicles are a DoD goal so that supply convoys in future conflicts can operate without human drivers, reducing potential casualties. An ACAP is well equipped to process the data from multiple sensors, combine that sensor data with map data, and then use its Intelligence Engines to execute AI algorithms for navigation and vehicle control. These are just a few examples of how AI at the tactical edge will transform defense systems, using power ful, new semiconductor architectures in rugged, SWaP- optimized packages.

• Cover