White Paper

WHITE PAPER A Generational Leap in Edge Computing with the Versal® ACAP mrcy.com 7 Processing for Complex Applications Defense applications usually involve multiple processing steps as sensor data is manipulated, analyzed and used to drive a response. For example, in EW systems, multi-step signal processing algorithms are used to extract waveforms from an antenna's input, then those waveforms are analyzed to find signals of interest. New advanced EW systems will add another processing level by using AI to create, in real time, countermeasures addressing those signals of interest. Optimized execution for each step requires a specific type of processor. In currently deployed systems, this is accomplished by using a set of specialized processor boards, with data moving between the boards using system backplane interconnects. These types of systems cannot meet the SWaP constraints of small platforms on the edge, while latency limits are dictated by the system-level interconnect. With an ACAP, this type of application processing can now be implemented within a single chip. All the processing engines can operate in parallel on a pipelined data stream that moves between engines using the NoC. On-chip data movement latency is at a level far beyond the capability of even the fastest multi-board system. DEVELOPING APPLICATIONS FOR ACAPS Tool Flexibility The Versal platform includes software development tools and offers flexibility that matches the device's multiple engine types. There are a range of options, so developers can use familiar tools and languages. Embedded software developers can program in C using the Xilinx Vitis™ software platform, and hardware engineers can continue to use Xilinx 's Vivado® tools to program in VHDL or Verilog. Moving AI Algorithms to an ACAP AI developers can use machine learning (ML) frameworks such as TensorFlow® or PyTorch® and target their C++ algorithms and Python data flows to the Versal ACAP without using the traditional tools needed to write RTL.* Making ACAPs Accessible for Aerospace and Defense Mercur y is the leader in adapting commercial technology to defense applications and platforms, making them more affordable, safe and secure. Through close collaboration with Xilinx, a highly valued technology par tner, we have designed a deployable processing module using the Versal AI Core ACAP at a ver y early point in our availability cycle. SWaP-optimized and ruggedized for operation in harsh environments, Mercur y 's ACAP-based solutions will bring new levels of application capability to the tactical edge. Mercury 's ACAP-based processing modules also conform to the latest MOSA (Modular Open System Approach) system interconnects. This ensures that ACAP solutions will have the interoperability needed for continual update capability. * RTL (Register Transfer Level) is a design abstraction used to model a digital circuit. An RTL description can usually be directly translated to an equivalent hardware implementation file for an ASIC or an FPGA.

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