Issue link: https://read.uberflip.com/i/1476562
WHITE PAPER Designer's Journey: Navigating the Transition to Versal ACAP mrcy.com 3 1. Kernel: A small unit of execution that performs a clearly defined function and that can be executed in parallel. AI Engine AIE Kernel AI Engine AIE Kernel AI Engine AIE Kernel Switch Switch Switch PL I/O PL I/O PL I/O HDL IP HDL IP Switch Switch Switch AIE Array FPGA Fabric Key x4 AXI streams 16 GB/s x2 AXI streams 8 GB/s User defined Cascade streams 48 GB/s x6 AXI streams 24 GB/s AIE Array Diagram THE JOURNEY BEGINS Adopting the Versal ACAP seemed challenging for our team at first. Having a primary background in traditional FPGA and DSP development, the idea of programming AIE processors using high-level languages was unfamiliar to us. In addition, we did not yet understand the available methods of defining the dataflow into and out of the AIE array. To dispel our worries, we decided to start small and build up our experience with AI. At a high level, the AIE array is similar to a GPU in that it consists of hundreds of vector processors. Each AIE processor can perform up to eight complex multiplications per cycle and has its own memory scratch pad for temporary storage of work. Data inputs and outputs are AXI4-Streams and can flow from the programmable logic into multiple AIE processors before being output from the AIE array. These functions executed by the AIEs are called kernels 1 , and a single AIE can share its time between different kernels. Each AIE processor has two physical stream inputs and outputs, however, these interfaces can be multiplexed to accommodate a higher number of "virtual streams." THE POWER OF VERSAL ACAP TECHNOLOGY IN A READY-TO-RUN, PROVEN AND TESTED PLATFORM Jump-start development with the Model 8258 low-cost 6U VPX platform to build, run and debug applications on the SCFE6931 Dual Versal ACAP processing module. Providing power and cooling to match the SCFE6931 in a small desktop footprint, the chassis allows access to all required front-panel interfaces and the optional rear-panel connectors to support 100 GigE. Mercury's Navigator® FPGA design kit (FDK) and board support package (BSP) complete the preconfigured development platform.