WHITE PAPER
Designer's Journey: Navigating the Transition to AMD Versal™ Adaptive SoCs
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INCREASING OUR UTILIZATION
To make better use of the processor 's time, we experimented
with increasing the number of beam outputs to discover how
throughput would be affected.
Improved Design: Simple Beamformer Kernel Stream
Ports Diagram
Doubled
Processing
Time
As shown below, the single AIE processor is now tasked more
than twice as efficiently. By reusing the element data with
more sets of weights to produce more beams, we greatly
increased our efficiency. However, this also meant that the input
throughput was reduced because we were now CPU bound.
Charting the throughput for designs with different numbers
of beam outputs illustrates the trade-offs that should be
considered when designing applications.
As we increased the number of beam outputs
from 4 to 5, the output rate showed a slight dip.
This is because the AIE's accumulator registers
could not hold all the results at the same time.
