White Paper

WHITE PAPER Real-Time Defense Systems Response Will Require PCIe 5.0 mrcy.com 4 A STANDARDS-BASED APPROACH TO RAPID GEN 5.0 INTEGRATION Defense system architects need a consistent pathway for technological upgrades, a way to rapidly integrate Gen 5.0 devices as they become available. To meet that need, Mercury is embracing the Open Compute Project (OCP) OpenEdge architecture. We will soon be introducing a portfolio of rugged, deployable "plug-and-pull" blade products based on that architecture, as an evolution to the highly successful RES HD server product line. Highly configurable, these products will exploit the snowballing ecosystem of OCP-based hardware, an ecosystem also implementing PCIe Gen 5.0. Building on an open standards-based platform will allow our customers to deploy rugged, Gen 5-capable servers without vendor lock-in. Mercury is committed to making our OCP-based platforms the fastest path to deploying PCIe Gen5 technologies on the battlefield. PCIE'S ROLE IN DEFENSE SYSTEMS PCIe is the computing industry 's most common interface standard for connecting high-speed components. In the commercial world, virtually every PC motherboard provides PCIe slots. PCIe is also an essential communication interface in commercial servers that support data centers and cloud applications. In these servers, PCIe is the primary data path from CPUs to both storage devices and to auxiliary coprocessing components, such as GPUs. The defense electronics industry adapts commercial technology to meet its needs, exploiting the continual performance increases driven by enormous market forces. As such, rugged server architectures are analogous to commercial server architectures, with PCIe occupying a central role in moving sensor data to archive storage, retrieving stored data for analysis and moving data to, and between, specialized computing components. PCIe 3.0 was a mainstay in rugged servers over the past decade; the majority of modern servers support Gen 3.0. However, expanding volumes of sensor data have pressured users to consider more capable protocols, such as PCIe 4.0, now implemented in most new deployed systems. While Gen 4.0 delivered twice the bandwidth of Gen 3.0, it is expected to be short-lived. Sensor data volumes continue to increase exponentially, while AI-based applications, with even greater bandwidth demands, are moving into active use. Another factor is the increasing speed of network connections, the primary mechanism for intersystem data communication. Ethernet is the universal fabric connecting data centers and rugged deployed systems. As Ethernet evolves into a terabit/s capable protocol, architects can expand the data paths between individual systems that may have previously been bottlenecks. Fortunately, the larger world of commercial electronics faces a similar set of challenges and is already moving forward with the greater bandwidth of PCIe 5.0. MOVING TO PCIe 5.0 PCIe 5.0 delivers twice the data throughput of Gen 4.0, reaching an effective bandwidth of 64 GB/s for a 16 lane (x16) link. While the Gen 5.0 specification was released in 2019, it has taken time for peripherals and semiconductors supporting this new spec to be developed. The first such devices were launched in early 2022, offering impressive capabilities. Two industry giants were among the first to bring Gen 5.0 products to market. Intel supports Gen 5.0 with its 12th Gen Core™ platforms and will soon be shipping even higher-performance Gen 5.0 CPUs in the Xeon® Scalable Processor™ line aimed at server systems. In parallel, NVIDIA is introducing new generations of GPUs and DPUs that use Gen 5.0 for both internal and external data paths.

• Cover