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WHITE PAPER Real-Time Defense Systems Response Will Require PCIe 5.0 mrcy.com 6 MORE DETAILS ON THE PCIE STANDARD PCIe is a standard defining communication between two devices over a point-to-point interconnect, or link, with each link having one or more lanes. Every lane has two signaling pairs, one pair for receiving and one for sending; that means every lane consists of four physical wires, or semiconductor traces. The PCIe standard defines links with 1, 4, 8, 16 or 32 lanes, though 32-lane links are rare. The lane count is written with an 'x ', so a 16-lane link is 'x16.' Lane count is often called 'width,' as in '16 lanes wide.' There are two different ways of measuring the performance of a specific link. One way uses the raw-bit transfer rate, usually expressed in terms of 'Gigatransfers per second' (GT/s). The other, more useful measurement reflects the effective transfer rate of actual data, or bandwidth. The data bandwidth is less than the raw transfer rate because a portion of the bits transferred are used for ensuring data integrity (encoding) and for other communication overhead tasks. The chart below shows these two measurement values for PCIe versions 1 through 6. As evidenced by this chart, the available data bandwidth doubles for each successive generation. And while PCIe 5.0 backplanes are backwards compatible with PCIe 4.0 devices and earlier devices, PCIe 5.0 devices must be used at both ends of a communication path in order to achieve full bandwidth afforded by the technology. Generation Bandwidth (x16) Gigatransfer per lane PCIe 1.0 4 GB/s 2.5 GT/s PCIe 2.0 8 GB/s 5 GT/s PCIe 3.0 16 GB/s 8 GT/s PCIe 4.0 32 GB/s 16 GT/s PCIe 5.0 64 GB/s 32 GT/s PCIe 6.0 128 GB/s 64 GT/s ENGAGE WITH MERCURY TO IMPLEMENT THIS NEXT-GEN TECHNOLOGY Start architecting your next generation of upgradable defense systems, based on the highest-bandwidth platforms available and using an ecosystem of the latest semiconductors. Our close collaboration with commercial technology leaders in the semiconductor industry means latest-generation innovations, like PCIe 5.0, can be rapidly integrated to push server- class processing to the tactical edge. To ensure rapid, cost-effective delivery of deployable solutions, Mercury has invested in scalable, U.S. manufacturing operations—a valuable trusted and secure section of the supply chain. We also see close cooperation with defense electronics visionaries, program managers and engineering teams as key to achieving maximum value for your solutions. Our system experts are focused on understanding your applications to develop an optimized system solution. Engage with the Mercury team to see demonstrations of our PCIe 5.0 technology and explore how we can best meet your deployed server requirements.

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