White Paper

WHITE PAPER Strategies for Deploying Xilinx's Zynq UltraScale+ RFSoC mrcy.com 3 Manpack (or womanpack) systems where the communications or direction finding equipment and associated power supply are worn by personnel are another target for SWaP reduction. Here again, smaller, lighter and less power is needed for making a practical, human carried system. RFSoC's high level of integration provides a significant amount of SWaP reduction when compared to designing the same functionality with discrete components. The example below shows the reduction in size by representing component footprints graphically. In the comparison, each component is roughly to scale, and space has been left between the discrete components to model a typical PCB layout, where ICs need space between them for assembly and placement of passive components. The RFSoC implementation can save 50% or more in overall size compared to the discrete approach. While RFSoC can reduce weight at the component level, that savings is minimal when you consider the total weight of nine ICs compared to a single RFSoC. Where weight savings can be appreciated is when you look at power. For every watt of power in a system, comes the weight of a cooling solution, either in metal or composite heatsinks, or in some systems, more exotic solutions like liquid and vapor cooling. RFSoC can easily bring power savings of 30%-40% or more compared to typical discrete solutions reducing the cooling solution complexity and weight. And in portable systems, every watt that can be eliminated results in smaller, lighter batteries and longer operation time. A key reason for the reduced power of RFSoC is the elimination of the interfaces needed to connect the various ICs in a discrete solution. Most data converters sampling at 1 or 2 GHz or higher depend on serial interfaces to move digital data between the converter and the FPGA. These interfaces expend power at both the data converter side and the FPGA side in serializing and deserializing (SerDes) circuitry. The most common serial interface protocol used for converters is JESD204. By integrating the converters directly into the FPGA, the serial interfaces are eliminated as well as data transfer latency which the SerDes process and protocol introduce. (More on serial vs. parallel converter interfaces and latency later in this paper) Another parameter often tacked on to SWaP is cost, sometimes referred to as SWaP-C. Here again RFSoC address the requirement. The same comparison used earlier of implementing the functions of the RFSoC as discrete components yields the following results: RFSoC (contains UltraScale+ FPGA, 8 A/Ds, 8 D/As and multi-core ARM processor) Multi- core ARM 2 Ch A/D UltraScale+ FPGA 2 Ch A/D 2 Ch A/D 2 Ch A/D 2 Ch D/A 2 Ch D/A 2 Ch D/A 2 Ch D/A Footprint required using discrete components Footprint required using RFSoC Figure 2 Discrete component vs. RFSoC solution size comparison. RFSoC (contains UltraScale+ FPGA, 8 A/Ds, 8 D/As and multi-core ARM processor) Multi- core ARM 2 Ch A/D UltraScale+ FPGA 2 Ch A/D 2 Ch A/D 2 Ch A/D 2 Ch D/A 2 Ch D/A 2 Ch D/A 2 Ch D/A Cost of discrete solution is 2x the cost of the RFSoC solution Figure 3 Discrete component vs. RFSoC solution cost comparison.

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