White Paper

WHITE PAPER Strategies for Deploying Xilinx's Zynq UltraScale+ RFSoC mrcy.com 4 > > > > > > > > > > > > The cost of a typical multi-core ARM processor + (4 x Dual 5 GSPS A/Ds) + (4 x Dual 10 GSPS D/As) + Kintex™ UltraScale+ FPGA (with equivalent programmable logic and DSP density of the RFSoC) = approximately 2x the cost of the same functionality delivered in a single RFSoC. While savings at any level is always welcome, the real benefit of the reduced cost can be seen in systems where many channels of A/Ds and D/As are required. Massive multiple-input multiple-output (MIMO) antennas are being targeted for applications from Wi-Fi to LTE to 5G. Massive MIMO antennas typically start at 8x8 configurations (8 receive channels and 8 transmit channels) and can be multiples of that configuration. This is a perfect match for the converters in the RFSoC. Another high channel count application is phased array radar. The Multi-function Phased Array Radar (MPAR) initiative combines the functions of several national radar networks into a single system for aircraft and weather surveillance. It is not uncommon for these antenna arrays to be specified with 64 or more elements, with each element requiring an A/D and D/A pair combined with signal generation and receive and control processing. With these systems as well as military surveillance and targeting systems where hundreds of elements can be required, the savings found in RFSoC's integrated solution can add up quickly. DATA CONVERTER INTERFACES Up to this point the advantages of RFSoC have been primarily in improving on already available solutions, saving on size, weight, power and cost compared to discrete component solutions. But by integrating the data converters into the FPGA, RFSoC offers a solution that is currently unavailable using existing technology. To understand this you must first look at how data converters connect to FPGAs. Using A/Ds as an example (but this is the same for D/As), connecting a 12-bit A/D to an FPGA using a parallel interface might look like this where each bit is represented by an LVDS pair and an additional pair is used for data ready or clock. In some cases the interface can make use of double data rate (DDR) technology where data is transferred on the rising and falling edge of the clock, effectively doubling the amount of data transferred in a single clock cycle. But even with DDR, parallel converter interfaces become problematic for data converters with sample rates above about 1.5 GHz due to the speed limitations of the LVDS interfaces on FPGAs. One solution to overcome this is to use a 1:2 demultiplexed interface (DeMux) where data is sent over two parallel interfaces each running at half of the sample rate. In the 12-bit A/D converter example, if the converter is sampling at 2 GHz, each of the 12-bit paths following the DeMux are running at 1 GHz. This keeps each 12-bit interface below the maximum clock rate allowed by the FPGA LVDS interface but still delivers the data needed to support the 2 GHz sample rate. 12-bit A/D Converter FPGA 12 data LVDS pairs > 1 clock LVDS pair Figure 4 A/D converter to FPGA interface using parallel LVDS pairs. Figure 5 A/D converter to FPGA interface using a 1:2 DeMux. > > > > FPGA > > Sample Clock 12-bit A/D Converter 1:2 DeMux > > 12 pairs @ 2 GHz 12 pairs @ 1 GHz 12 pairs @ 1 GHz Clock LVDS Outputs 1 st half sample 2 nd half sample Clock

• Cover