WHITE PAPER
Designer's Journey: Navigating the Transition to AMD Versal™ Adaptive SoCs
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IMPLEMENTING THE DESIGN
Each AIE application consists of a dataflow graph
3
that
describes a set of kernels and their associated inputs, outputs
and interconnections. For standalone simulation of an AIE graph,
these input and output ports reference test vector files. We
began testing our first application by generating test element
data and weights with MATLAB®. These test vectors represented
the input data that would normally flow from the programmable
logic fabric.
REVIEWING OUR INITIAL AIE DESIGN
After simulating our AIE kernel, we used the AMD Vitis™
analyzer tool to display the trace data generated. This timeline
display allowed us to see the activity of each AIE in the array
and how effectively it was being utilized.
3. Dataflow graph: A dataflow graph is how an AI Engine application is described at the highest level. Dataflow graphs consist of nodes and edges where nodes
represent compute kernel functions and edges represent data connections.
Initial Design: Simple Beamformer Kernel Stream Ports Diagram
Input: ElementsEven
Interleaved samples
from even elements:
#2, #4, #6 …
Input: Weights
Beamforming weights.
Output: Beam
Complex beam samples.
Input: ElementsOdd
Interleaved samples
from odd elements:
#1, #3, #5 …
As shown here in the debug
screen, we added debug
printf() statements inside our
C++ kernel code to print the
inputs and calculation results
for the first few elements.
Idle Time
Processing Time
As shown in the AMD Vitis™ analyzer screen below, our first
kernel spent a substantial amount of its time idle. This is
because the AIE was able to compute the output beam faster
than the I/O throughput rate.
