White Paper

w w w. m r c y. c o m WHITE PAPER Traditional die stacking design topologies have their limits Traditional multi-chip stacking design methodologies use a branch topology where multiple transmission lines are routed from the same electrical node. This is an effective design method for DDR2 and DDR3 devices as it enables the required data rates and densities those generations of devices can deliver. Skillfully designed stacked DDR4 devices are feasible with this method, as seen in Mercury's 4GB DDR4 device. However, there are inherent limitations for high capacities as the increased termination path or bus length causes signal distortion and limits the maximum bandwidth of the transmission line due to reflections. Figure 3. DDR die stacking and wire bonding using branch topology with stubs As the number of die stacked increases, these parameters continue to degrade to a detrimental point. Branch topology reaches its maximum capability thereby ruling out this method for use in highly dense, high- speed DDR4 and DDR5 devices. SI engineers must look at alternative design meth- odologies to enable the next generation of smaller, more agile military systems for the highest density DDR4 and DDR5 devices. In the remainder of this white paper, we present our new design methodologies to achieve these goals, previously deemed impossible. Edge processing architectures in today's autonomous and AI military systems process an ever growing amount of sensor data. Many of these systems or devices used for edge processing applications in forward-deployed environments need to be small, rugged and agile. To handle this extreme workload, system architects must design boards using the fastest field programmable gate array (FPGA) devices and multicore processors. These devices cannot provide peak performance without massive amounts of high-speed DDR4 memory for resident data and real-time execution. Faced with additional challenges, the system architect must design these systems to meet the size, weight and power (SWaP) constraints of smaller, more agile edge processing platforms integral to our warfighters' mission success. To support the system requirements, each embedded board within the system could need a minimum of 64GB of memory per processor, equating to more than 128 separate commercial-grade memory devices or multiple dual inline memory modules (DIMM) for layout on a printed circuit board. This is not a feasible solution for the embedded boards at the core of ultra-compact edge processing architectures in military systems operating in harsh, forward-deployed environments. High- density, military-grade memory manufactured with state-of-the-art 3D packaging technology must be utilized for space and power savings while maintaining reliability in harsh environments. Design engineers commonly assume that no design methods exist to package enough die to create an ultra-compact microelectronic device such as a single 16GB DDR4 component while simultaneously achieving and maintaining high-speed data rates and device reliability. Meeting future DDR5 speeds of 6400 Mbps while sustaining signal integrity (SI) in a single compact device will be impossible if this assumption is true. This principle was true, until now. In this white paper, we introduce two new design topologies that reject the conventional wisdom of die stacking limitations thereby enabling the next generation of SWaP-optimized military intelligent sensors. The problems are stacking up The complexity of die stacking and wire bonding increases with each additional die needed to design high-density memory, such as a single 16GB DDR4 device or a custom multi-chip module (MCM) device. With so many circuits in a tightly stacked configuration, signal integrity is at the forefront of design considerations. While a comprehensive discussion of SI is beyond the scope of this white paper, we can highlight its importance. The two main components of compromised SI in the context of this discussion are crosstalk and return loss performance. • Crosstalk is the unwanted voltage noise coupling due to strong mutual inductance and mutual capacitance. More simply stated; it is the interference to a signal in one circuit caused by the signal transmission in an adjacent circuit in the die stack. • Return loss is the loss of signal energy due to impedance dis- continuities, which reflect a portion of the signals energy back to its source instead of carrying through to the final termination. Left unaddressed, these performance issues limit data speeds in stacked memory devices, thereby comprising overall system performance and reliability. In mission-critical military applications, this can lead to catastrophic events. 2 Signal A Crosstalk Signal B Incident Voltage Incident Voltage Reflected Voltage Reflected Voltage Return Loss = Transmitted Voltage Device Under Test (DUT) Figure 1. Crosstalk Figure 2. Return loss

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