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3 Eye diagrams are used in this paper to show the quality or bit-error performance of the high-speed digital signal(s). Each eye diagram provides a visual representation of millions of transmitted bits, with signal amplitude on the vertical axis and unit interval (UI) or bit period on the horizontal axis. As digital signals are degraded by frequency dependent losses such as crosstalk, the actual signal deviates from the ideal signal. The deviation from the signal amplitude is called noise, and deviation from signal time is called jitter. These unwanted frequency-dependent losses compromise signal quality, ultimately reducing the signal-to-noise-ratio (SNR) below receiver detection thresholds and producing bit errors. The diamond in the center represents the bit error compliance mask with both minimum amplitude and minimum bit period limits. If any bits violate the bit error compliance mask, the digital signal fails to meet the minimum performance requirements. High-density DDR4 innovation realized Now to reach the high-speed requirements of DDR4, SI engineers face two main challenges: (1) Reducing crosstalk, prominent with designs using non-transverse electromagnetic (TEM) conduits such as a redistribution layer (RDL) and bond-wire. (2) Meeting a minimum of -12 dB return loss performance. The solution: Enhancements to the interconnect layer by way of a co- planar topology that supports higher frequency operations than branch topology. This method shortens the path between the two terminations while eliminating stubs, consequently improving signal integrity and timing. To achieve this, routing signal paths sequentially from one die to the next eliminates reflections associated with stubs or extra traces previously seen in branched designs. High-speed data rates are achieved through the creation of a contiguous signal return path and linear bus path by using microstrip transmission line technology. Addi- tionally, considerations made to signal and return path trace geometry further enable higher data rates and improvements to return loss. With this topology, achieving a return loss of -16 dB through a delicate balance with crosstalk enables the miniaturization of 18 memory devices in a single compact package while offering 2666 Mbps date rates over military temperature ranges. (See figure 8). With this achievement, Mercury introduced the first 16GB DDR4 device. However, while return loss is optimized with this method, improvement to crosstalk performance is still needed to meet DDR5 data speeds. Figure 4. 2400 Mbps DDR4 using branch topology Figure 5. 4400 Mbps DDR5 using branch topology Figure 6. 4400 Mbps DDR5 using advanced coplanar topology Figure 7. 6400 Mbps DDR5 using advanced coplanar topology

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